Faculty Achievements
Research Publication Details
S.No | Name of the faculty | Title of the paper | Journal | ISSN/ISBN/IF/ Publication Index |
1 | Dr. Rohini Deshpande, Deepak Deshpande | FIR notch filter with rejection bandwidth tuning and sharpening Book series of Frontiers in Artificial Intelligence and Applications | FAIA | Vol. 299, pp.364 – 3371. December 2017 DOI:10.3233/978-1-61499-828-0-364 |
2 | Rani Aishwarya SN | Robust object tracking using kernalized correlation filters(KFC) and kalman predictive estimates | IEEE International | 19 May 2017 |
3 | Vinay B. E, Dr.RohiniDeshpande and Pallaviram Sure | Design of rectena for energy harvesting from ambient GSM and WLAN frequency bands | RUAS-SASTech Journal | Vol.15, Issue 2, September 2016 |
4 | Archana B R, Dr. Rohini Deshpande |
Modeling of multiplier and adder architecture for an efficient fir filter design | IJTRE | Vol.2, Issue 10, June 2015. |
5 | ShrutiKodiya, Dr.RohiniDeshpande | Design of efficient sum of absolute difference architecture for H.264/AVC video coding | IJTRE | Vol.2, Issue 10, June 2015. |
6 | Archana B R, Dr. Rohini Deshpande |
A review paper on modeling of multiplier and adder architecture for low power digital FIR filter | IJTRE | Vol.2, Issue 9, May 2015. |
7 | Farah, Dr. Rohini Deshpande | Cloud network based smart home system using Rashberry PI | IJTRE | Vol.2, Issue 9, May 2015. |
8 | Manjula C, Dr.D.Jayadevappa | FPGA based digital logic analyser for digital automatic test equipment | IJFGCN | Vol.12, ISSN No. 2233-7857 PP 306-318,2019 Scopus Indexed |
9 | Manjula C, Dr.D.Jayadevappa | FPGA based clock frequency sensor and range estimating system for testing memories and processors | IJEET | Vol.11, Issue 5 July 2020 Web of Science |